1. Field of the Invention
The present invention concerns a method of producing an electro-optical device in which thin film transistors are formed and, more in particular, it relates to a technique capable of reducing the number of photolithographic steps as compared with that in the prior art method.
2. Description of the Related Art Statement
FIG. 165 shows an example for a constitution of an equivalent circuit of an active matrix liquid crystal display device using thin film transistors as switching elements.
In FIG. 169, a plurality of gate wirings G1, G2, - - - , Gn and a plurality of source wirings S1, S2, - - - , Sm are wired in a matrix, in which each of the gate wirings G is connected to a scanning circuit 1 and each of the signal wirings S is connected to a signal supply circuit 2 respectively. A thin film transistor (switching element) 3 is disposed to a crossing point between each of the wirings and a capacitance section 4 as a capacitor and a liquid crystal device 5 are connected to a drain electrode of the thin film resistor 3 to constitute a circuit.
FIG. 170 and FIG. 171 illustrate an example for a structure of a thin film transistor array substrate having portions, for example, the gate wirings G and the source wirings F on a substrate in an existent active matrix liquid crystal display device shown by the equivalent circuit in FIG. 169.
In the thin film transistor array substrate shown in FIG. 170 and FIG. 171, the gate wirings G and the source wirings S are wired in a matrix on a transparent substrate 6 such as made of glass. Further, a thin film resistor 3 is disposed near the crossing point between each of the gate wirings G and the source wirings S.
The thin film transistor 3 shown in FIG. 170 and FIG. 171 has a general etch-stopper type constitution formed by disposing an gate insulator film 9 on the gate wiring G and a gate electrode 8 led out of the gate wiring G, disposing a semiconductor film 10 made of amorphous silicon (a-Si) on the gate insulator film 9 and further disposing, on the semiconductor film 10, a drain electrode 11 and a source electrode 12 made of an electroconductive material opposing to each other. An ohmic contact film 10a comprising, for example, amorphous silicon and doped at a high concentration with an impurity as such as phosphorus as a doner is formed to the uppermost layer of the semiconductor film, on which an etching stopper 13 is formed being put between the drain electrode 11 and the source electrode 12. Further, the gate electrode 8 has a double structure comprising a gate insulator film 8a of an upper layer and a gate wiring 8b of a lower layer, and a transparent pixel electrode 15 made of a transparent electrode material is formed from a portion above the drain electrode 11 to lateral sides of the drain electrode 11.
Then a passivation film 16 is disposed covering, for example, the gate insulator film 9, the transparent pixel electrode 15 and the source electrode 12.
A not illustrated orientation film is formed on the passivation film 16, and liquid crystals are disposed above the orientation film to constitute an active matrix liquid crystal display device 15 and the device can control the orientation of liquid crystal molecules when an electric field is applied to the molecules of the liquid crystals by way of the transparent pixel electrode 15.
By the way, the thin film transistor array substrate of the structure described above has been produced so far based on the steps as described in Table 1 shown below.
TABLE 1 ______________________________________ Step Production method Material Remarks ______________________________________ Initial cleaning Brush and UV Formation of surface Reactive sputtering TaOx 750 nm stabilization layer Formation of gate DC sputtering Al 200 nm wiring metal Gate wiring metal PL1 Wet etching Formation of gate DC sputtering Ta 400 nm electrode Gate electrode PL2 Dry etching Anodization of gate TaOx 300 nm electrode Formation of gate Plasma CVD SiNx 250 nm insulation Formation of a-Si Plasma CVD a-Si 50 nm Formation of ES Plasma CVD SiNx 100 nm insulator layer ES insulator layer PL3 Wet etching Back exposure method Formation of SD Plasma CVD n + Si 25 nm semiconductor Device area PL4 Dry etching Formation of SD DC sputtering Ti 400 nm electrode SD electrode PL5 Dry etching Formation of transparent Reactive sputtering ITO 50 nm electrode Transparent electrode Wet etching PL6 Formation of Plasma CVD SiNx 250 nm protection layer Protection layer PL7 Wet etching ______________________________________ Note: PL: photolithography, ES: etching stopper, SD: source/drain 1-7: Exposure process
At first, a transparent substrate, for example, made of glass is prepared, and then put to initial cleaning by a brush cleaning device and an UV-irradiation device, and a surface stabilization film, for example, made of TiO.sub.x is formed by using a film-forming method such as reactive sputtering on the transparent substrate after cleaning.
A metal film for gate wirings made of an electroconductive material such as Al is deposited on the substrate formed with a surface stabilization film by using a film forming-method such as DC sputtering, and the metal film is etched in a first photolithographic step (1) using a method such as wet etching, to form gate wirings.
Then, a metal film for forming a gate electrode made, for example, of Ta is deposited on the gate wirings by a film forming method such as DC sputtering and then the metal film is etched in a second photolithographic step (2) using a method such as dry etching, to form the gate electrode.
Then, the gate electrode is anodized to form the surface portion into TaO.sub.x to apply a treatment for improving the insulation performance of the gate electrode.
Successively, a gate insulator film made of SiN.sub.x, a semiconductor film made of a-Si (amorphous silicon) or the like and an insulator film for etching stopper made of SiN.sub.x are formed on them by a film-forming method such as plasma CVD.
Then, etching is applied in a third photolithographic step (3) using a method, for example, of wet etching to form an etching stopper on the gate electrode.
Then, an ohmic contact film such as made of a-Si(n.sup.+) is formed on the surface of the substrate after the third photolithographic step by using a method such as plasma CVD.
Then, the semiconductor film and the ohmic contact film are patterned in a fourth photolithographic step (4) using a method such as DC sputtering to form a semiconductor portion above the gate electrode in a state isolated from other portions.
Then, a metal film made, for example, of Ti is formed on the surface of the substrate after the fourth photolithographic step by using a film-forming method such as DC sputtering.
Then, the metal film is patterned in a fifth photolithographic step (5) using a method such as dry etching to form a source electrode and a drain electrode.
Then, a transparent conductive film, for example, made of ITO (Indium Tin Oxide) is formed on the surface of the substrate after the fifth photolithographic step by a film-forming method such as reactive sputtering.
Then, the transparent conductive film is fabricated in a sixth photolithographic step (6) using a method such as wet etching to form a transparent pixel electrode, and then a protection film, for example, made of SiN.sub.x is formed on the surface of the substrate after the sixth photolithographic step by a method such as plasma CVD.
Then, a seventh photolithographic step (7) of patterning the protection film by a method such as wet etching to form a contact hole for a source terminal for connection with the source electrode and a contact hole for a drain terminal for connection with the drain electrode, to complete the thin film transistor array substrate.
However, when the thin film transistor array substrate is produced by the method as described above, photolithographic steps have to be applied for seven times and, since there are a number of photolithographic steps, they give a significant effect by so much on the yield to bring about a problem of increasing the production cost.
Then, in a case of producing the thin film transistor array substrate of this type, it may be adopted a structure in which various thin films are stacked, a contact hole is formed to a portion of the laminate film, and a conductive film is formed to the contact hole to electrically connect the film of the upper layer with the film of the lower layer by way of the conductive film.
FIG. 172 shows an example of such a structure in which an insulator film 18 made, for example, of SiN.sub.x and a conductive oxide film 19 made of ITO are stacked on a metal film 17, for example, made of Ti formed on the substrate, and the conductive oxide film 19 is connected with the metal film 17 by way of a contact hole 18a formed to the insulator film 18.
In the structure of this example, the contact hole 18a is formed by a method of forming the insulator film 18, depositing thereover a predetermined pattern of a photoresist, etching the insulator film 18 by dry etching using, for example, SF.sub.6 +O.sub.2 gas to form the contact hole 18a, and then peeling off the photoresist with O.sub.2 plasma and subsequently forming the conductive oxide film 19. However, since the metal film 17 is exposed through the contact hole 18a to an oxidative atmosphere in the course of the process, there is a worry that the metal film 17 is oxidized.
In view of the above, Ti has been used so far as a metal capable of providing a good contact with the conductive oxide film 19 and is less oxidized by the O.sub.2 plasma atmosphere but a thin film of Al or Ta which is oxidized more readily than Ti can not be used, so that the material used for the metal film 17 suffers from restriction. By the way, in a case where a contact area of the connection portion is set to 7 um.sup.2 and a contact chain of a structure having 1,600 steps for the contact portion of the structure shown in FIG. 172 is formed, the contact resistance of the thin Al film to the thin ITO film is from 10.sup.10 -10.sup.12 ohm, whereas the contact resistance of the Ti thin film to the ITO thin film is from 10.sup.4 to 10.sup.5 ohm and the Ti thin film is apparently superior in the contact performance. It is considered that exposure to the O.sub.2 plasma atmosphere forms oxide layers at the boundary of the connection portion and, even if Ti has lower conductivity as compared with that of Al, it contrarily shows less contact resistance than the latter due to the presence of the oxide layers.
Further, in a case of using the thin Ti film as the metal film 17 described above, if the structure is applied to a thin film transistor array substrate to form gate wirings with the metal film 17, the Ti metal film 17 can be served for usual application use but it may possibly cause signal delay in the gate wirings since the specific resistivity of Ti itself is high, to result in a disadvantage in view of increase for the size of a liquid crystal panel.